Nvidia, a leading designer of chips for AI and ML acceleration, has developed a new system called AutoDMP that utilizes AI to accelerate chip design. The company recently released a paper and blog post discussing the system’s use of GPU-accelerated AI/ML optimization in chip floor-planning, resulting in a remarkable 30X improvement in speed compared to previous methods. This advancement is poised to revolutionize chip design and boost the effectiveness and functionality of contemporary chip technology.
To speed up the process of placing building blocks in processors, a crucial task in chip design, Nvidia has developed AutoDMP or Automated DREAMPlace-based Macro Placement. AutoDMP is capable of being incorporated into an Electronic Design Automation (EDA) system used by chip designers and utilizes AI to automate the discovery of the most efficient placement of building blocks.
Nvidia has showcased the effectiveness of AutoDMP by utilizing it to determine the most optimal layout for 256 RSIC-V cores, which consists of 2.7 million standard cells and 320 memory macros. In only 3.5 hours, AutoDMP managed to determine the most efficient configuration on a single Nvidia DGX Station A100, highlighting its rapidity and efficiency in chip design.
According to Nvidia, the placement of building blocks in processors, or macro placement, plays a critical role in determining several design metrics like area and power consumption. This makes optimizing macro placement an important design task that can significantly impact a chip’s performance and efficiency, ultimately affecting the customer experience. AutoDMP’s AI-powered automation of the optimization process can assist chip designers in improving the performance and efficiency of their designs, resulting in better outcomes for customers.
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AutoDMP leverages an analytical placer that frames the macro placement problem as an optimization challenge, aiming to minimize wire length while adhering to the placement density constraint. This problem is then solved using numerical methods. To speed up the optimization process, AutoDMP utilizes GPU-accelerated algorithms, offering a 30-fold increase in speed compared to previous placement methods. AutoDMP is also capable of accommodating cells of various sizes, providing greater design flexibility. The animation illustrates AutoDMP’s placement process, where macros (red) and standard cells (gray) are placed within a restricted area to reduce wire length, demonstrating the tool’s capability to optimize the placement process.
Moreover, AutoDMP is an open-source tool, and its code can be accessed on GitHub, providing further access to the chip design community.
Nvidia‘s AutoDMP is one of many chip design tools to utilize AI for optimal chip layouts. Synopsys’ DSO.ai automation tool, already applied in 100 commercial tape-outs, was previously discussed in February. Synopsys positioned its solution as an “expert engineer in a box” and emphasized its suitability for contemporary multi-die silicon designs.
The purpose of Synopsys’ DSO.ai automation tool was to alleviate engineers’ monotonous duties and permit them to concentrate on more inventive responsibilities. Despite the fact that both Synopsys and Nvidia intend to automate the chip design process, they have differing methods. While Synopsys promotes DSO.ai’s capacity to free engineers from tedious work, Nvidia highlights the benefits of AutoDMP in terms of both speed and quality for chip design.
AI-based chip design tools are becoming increasingly popular, with many companies exploring their potential. For instance, Google has leveraged machine learning for its Tensor Processing Units (TPUs), specialized chips designed for running machine learning models. Google also recently released a research paper that proposed using deep reinforcement learning to generate chip floorplans.
AI-based chip design tools such as AutoDMP and DSO.ai are becoming more prevalent as chip designers aim to optimize the design process and create more efficient and performant chips. These tools can reduce the time and cost associated with chip design while improving product quality. As more companies experiment with AI in chip design, we expect further advances and innovations in this space in the coming years.