Graphics Cards

EPYC Genoa CPUs now shipping with 2DPC memory support

AMD‘s upcoming EPYC Genoa server processor has been reported to have a 2DPC memory constraint issue, limiting the number of memory modules used in a server system. 

The 2DPC memory constraint on the EPYC Genoa CPU results from AMD‘s design prioritization of other performance factors.

While this constraint may limit the total amount of memory installed in a server system, it is intended to ensure that the installed memory operates at the highest possible speed.

Mark Papermaster, AMD’s CTO, was questioned about the 2DPC memory constraint issue of the EPYC Genoa CPUs at a Morgan Stanley investor conference.

The 2DPC memory constraint limits the number of memory modules installed in a server system, and Papermaster acknowledged the issue. However, he also explained that the memory constraint is a necessary trade-off for maintaining the CPU’s high-speed memory interface.

The limitation results from AMD’s design choices prioritizing other performance factors in the EPYC Genoa CPU. While the 2DPC memory constraint may create challenges for server system designers, it is a deliberate design decision made by AMD to ensure that the installed memory operates at the highest possible speed while prioritizing other performance factors.

During the investor conference hosted by Morgan Stanley, Mark Papermaster provided further details on the 2DPC memory constraint issue associated with the EPYC Genoa CPUs.

He clarified that this limitation is intended for a smaller group of customers who require specialized high-speed memory configurations and will not affect most customers.

Papermaster also indicated that the speeds for these customers would be announced later in the quarter and would increase as necessary. He further emphasized that the 2DPC memory constraint is a specialized feature intended to cater to the specific requirements of a niche customer segment, and it will not significantly impact most customers.

AMD reassured that no new chips must be manufactured to address the 2DPC memory constraint issue on the EPYC Genoa CPUs. Instead, the issue can be resolved through BIOS updates, with AMD reportedly issuing multiple updates to OEM clients. The updates are expected to enable 2DPC configurations by the end of Q1.

Customers who require 2DPC configurations can resolve the issue through a software update rather than replacing the hardware.

However, it’s worth noting that, at present, only one platform from Tyan is available for sale that supports 2DPC configurations. This means that the availability of compatible platforms remains limited. Customers who need this feature may have to wait until more options become available in the market.

While the news of not needing new chips to replace the current product is positive, it’s important to remember that the issue still needs to be entirely resolved. The availability of compatible platforms must improve to make this feature accessible to more customers.

After Tom’s Hardware sought clarification regarding Papermaster’s statement, AMD clarified that the information pertains to systems supporting the new 2DPC configurations, necessitating more memory slots.

This clarification was vital because it helped to differentiate between the 2DPC configuration issue and Papermaster’s statement. In other words, Papermaster was not referring to the new systems that require more slots but rather a specific set of customers who require high-speed memory configurations, which is a separate issue. This distinction is crucial because it helps avoid confusion and ensure customers understand the topic clearly.

Last year, AMD released its EPYC Genoa server processors with support for twelve-channel DDR5 memory and various innovative interfaces. However, the initial configuration only permitted a single DIMM in each channel, limiting the usage of a single memory stick for each twelve-channel DDR5 controller.

To address this limitation, AMD has announced that it will release a BIOS update in the first quarter of 2023.

This update will enable dual DIMM support per each memory channel or 2DPC (two DIMMs per channel), increasing the memory channels’ capacity on the EPYC Genoa processors. This update will give customers more memory configuration options and improve their systems’ flexibility.

Moreover, AMD has announced that it will also offer updated configurations to enhance the speed of 2DPC memory. This update will significantly improve the initial configuration’s performance and benefits customers requiring high-performance memory solutions for their server workloads. This update is expected to be well-received by customers and help improve the EPYC Genoa processor’s overall functionality.

SemiAccurate hinted at issues with AMD’s EPYC Genoa chips in June 2022, later revealed to be a subsystem glitch. AMD delayed redesigning and respin, opting for a BIOS update instead. Tyan listed a Transport CX GC68A-B8056 barebones rackmount with 2DPC support.

The performance difference caused by the BIOS is known once the newer variants are released, but 2DPC speeds are expected to be limited.

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